Speed and power are the major performance metrics of digital circuits, especially microprocessors which are the major drivers for sub-100 nm CMOS technology. However variation in threshold voltage during fabrication causes a wide variation in the speed and leakage power both within-die (WID) and die-die (D2D). This in turn affects the yield of the chips, that meet certain performance specification. The common solution to this problem is to design the circuit for worst case variation. However this is too pessimistic and will result in a large degradation in the performance of the chip. This is because only a small fraction of the millions of transistors in the die need to be tuned to meet the target power and performance. The major challenge in circuit design lies in controlling these devices selectively and adapting them to work efficiently in a specific process corner. In this aspect the dynamic gates draw a lot of attention. Dynamic circuits have found a widespread use in microprocessors and other high speed designs because of their lower logical efforts compared to the other logic styles such as static CMOS. A static CMOS implementation requires the use of a PMOS and an NMOS transistor for each input. Also the PMOS has to be sized larger compared to NMOS, to get the same drive strength. Thus for wide AND-OR like structures the load capacitance on each input becomes very high. However the dynamic circuits use a clocked pre-charge transistor and a bottom pull-down NMOS stack to implement a given logic. FIG. 1 shows a typical domino gate topology, where f represents a wide AND-OR NMOS logic. In the negative half cycle of the clock φ (pre-charge phase) the dynamic node is pre-charged high through the PMOS transistor. During the positive half cycle (evaluation phase) the dynamic node is either discharged or is held high based on the input data. Thus when the node is floating high in evaluation phase, it is susceptible to leakage and other coupling noises. For a wider pull-down logic the leakage through the NMOS pull-down legs can destroy the state of the floating node. To avoid this a keeper transistor is normally used with an inverter feedback to hold the state of the dynamic node. There are certain tradeoffs involved in designing the keeper.
FIG. 2 shows a wide AND-OR domino gate with a conventional keeper, consisting of a weak PMOS and a feedback inverter, that is traditionally used to hold the state when the pull-down stack is OFF during evaluation. However in technologies below 130 nm, the leakage current has increased tremendously and the variation in the device threshold has also gone up. Further, the increasing functionality on the chip demands a wider pull down logic. The above factors pose a requirement that the keeper should be strong enough to hold the dynamic state in the fast corner when the pull-down stack is OFF.
Also in the slow corner the contention current from the keeper should be less than the ON current of a single pull-down leg for the dynamic node to switch its state. These conditions require that the keeper should have a good tracking over different process corners and must have scalability with the increasing pull-down width.
In case of conventional keeper technique the keeper is on at the start of the evaluation phase. If one of the pull-down legs turn on, a large contention current flows through the keeper that slows down the falling transition. As the dynamic node comes down, the keeper PMOS goes from linear region to saturation region resulting in an increasing contention current until the output of the feedback inverter rises sufficiently to turn off the keeper. In case of wider gates if the keeper is sized for the worst case leakage it can result in a situation where the contention current exceeds the on current of a single NMOS and prevent the node from switching. Another important metric of the dynamic circuits is the robustness of the gate to power supply variation and other coupling noises. A linear increase in noise voltage at the gate causes the leakage current to increase exponentially and hence the keeper has to be designed accordingly to achieve the target robustness of the gate. In case of conventional keeper, the noise robustness can be improved by increasing the keeper size. This causes the delay of the dynamic gate to increase exponentially.
The keeper upsizing also has a severe impact on the power. Excess power is wasted in the keeper due to a large contention current and in the feedback inverter due to short circuit current because of the longer fall time of the dynamic node voltage. The conventional keeper cannot be used for wider pull-down legs because the keeper size required to maintain the robustness is too huge that during evaluation the logic fails to switch due to the larger contention current. Thus upsizing the keeper is certainly not the right way for achieving robustness. Also the variation in the NMOS leakage is not tracked by the PMOS keeper.
Techniques [1] [2] [3] propose a process tracking conventional keeper design, where in the dynamic node is loaded with a number of parallel keepers of unit width. These keepers can then be turned on selectively based on the process corner. The corner information is obtained from an additional circuitry which in turn generates digital codes to control the keepers. This technique still has the problem of contention and also a large area overhead to generate the corner information.
Techniques [4] [5] suggest a method for reducing the contention during evaluation period. The input data to the wide dynamic gates are ready before or close to the start of the evaluation phase. In such a case, the maximum time window for any potential output transition is only a fraction of the total evaluation time. The conventional keeper turns on unconditionally at the start of the evaluation phase, degrading the performance of the gate. However in the conditional keeper technique, the keeper is weak during the output transition window and strong for the rest of the evaluation time, if the dynamic node should remain high. The weak keeper during the transition window results in reduced contention and a faster output transition, while the strong keeper during the rest of the evaluation time results in a good robustness to leakage and noise.
Technique [6] proposes a replica current mirror method that tracks the various process corners very closely. A replica of the pull-down stack generates a reference leakage current, which in turn is mirrored into the dynamic node to compensate for the leakage. The replica NMOS has a width equal to that of the pull-down logic. The gate of the replica transistor is connected to VSS through a diode connected PMOS at the top. The PMOS mirror voltage is then used to control the keeper current. The mirror voltage varies based on the process corners. This technique can track the systematic process variations in the chip. Another advantage of this design is that the same replica circuit can be used to mirror the current to several other dynamic gates of same equivalent width.
The limitations of the prior art techniques are explained below.
1. The conventional keeper design results in huge contention current and lacks process tracking. This has limited the number of pull-down legs in the nano-CMOS technologies.
2. The process tracking keeper technique [1] has significant contention current during the evaluation phase. Also since the keeper dimensions are fixed, finer control of the keeper current is not possible. Moreover this technique does not track the dynamic variations in temperature and noise.
3. The conditional keeper technique [4], although reduces the contention current by delaying the clock to the strong keeper, lacks process tracking. The inverter delays do not track the process corners. Also with increasing noise robustness required at the gate, the conditional keeper turns on early and it tends towards a conventional keeper in its performance.
4. The current mirror technique [6] closely tracks the process corners. However in a given process corner the amount of contention is still high due to the feedback keeper.
5. The feedback keeper technique in general results in a lot of short circuit power dissipation in the keeper PMOS and also in the feedback inverter.
6. The area overhead in case of current mirror technique is large. In order to achieve a better process tracking the keeper should be in close proximity to the pull-down logic. If a single current mirror is used for the entire design then it can result in variation in the bias currents.
7. There is a tradeoff between the performance and noise immunity of the dynamic gates. Higher the noise immunity required larger is the delay.